Intel funds silicon photonics foundry service -

Intel's supporting a new University of Washington programme designed to dramatically cut the cost of manufacturing silicon photonic chips.

The Optoelectronics Systems Integration in Silicon (OpSIS) project will allow 'shuttle runs', in which researchers cut costs by sharing silicon wafers between multiple projects. A single circuit design might use only a few square millimetres, says assistant professor of electrical engineering Michael Hochberg, so that shuttle runs can cut costs by more than 100 times.

“We would like the photonics industry, 10 years from now, to function in a way that’s very similar to the electronics industry today,” he says. “People building optoelectronic systems will send designs out to an inexpensive, reliable third party for manufacturing, so they can focus on being creative about the design.”

In developing the rules and protocols, the team aims to ensure that even non-specialists can design and build functioning chips that integrate photonics and electronics.

“You want a minimum of rules because people are going to use the technology in ways that you never imagined,” says Carver Mead, professor emeritus at the California Institute of Technology. “You want people to use it in ways that seem crazy.”

Silicon photonics provides a faster, lower-power means for moving data around than electrons; a single optical fiber or waveguide can carry many terabits per second of data.

Companies including Intel and IBM have made major breakthroughs in the technology over the last year.

“OpSIS will enhance the education of US engineering students, giving them the opportunity to learn the new optical design paradigm,” says Intel's chief technology officer, Justin Rattner.

“The ability to produce such low-cost silicon chips that manipulate photons, instead of electrons, will lead to new inventions and new industries beyond just data communications, including low-cost sensors, new biomedical devices and ultra-fast signal processors."

OPSIS has already signed up a few early users who are participating in so-called 'risk runs' to test the new protocols.

One such is John Bowers, a professor of electrical and computer engineering at the University of California, Santa Barbara who has designed a circuit for the first run.

“By focusing research of many different groups in one process line, that allows you to advance a library of components and processes faster than any one group could do on its own,” Bowers said. “It enables a faster evolution of photonic devices.”

Eventually, the centre plans to offer three runs per year, each of which could accommodate 30 to 40 users. The chips will be built by BAE Systems.