AMD shows off Orochi die, talks more Fusion

Chekib Akrout, senior VP of the technology group, AMD, kicked off the first customer talk at GloFo's GFC2010 conference and revealed more about its Llano Fusion technology, as well as showing off a future "Orochi" die which will have eight cores.

Apologies in advance for the quality of the pictures. Charlie D has a much better picture of the Orochi die, here.

Akrout said that AMD needed a foundry approach that can unite both GPU and CPU - for example GloFo is building the Llano chip, scheduled for 2011, while TSMC is its partner for the Ontario die, due out later this year.

He said that Fusion is well suited to parallel compute video and digital media files.

He said that When you bring the CPU and GPU together it gives a high speed bus  architecture and a shared low latency memory model. Bringing the two  together will let the existing architectures be exploited and giving  parallel compute.

Global Foundries CEO, Doug Grose, admitted that yields at 32 nanometre were still not right, but he showed off a wafer that he said demonstrated how rapidly AMD's foundry was moving on the technology.



When you bring the CPU and GPU together it gives a high speed bus  architecture and a shared low latency memory model. Bringing the two  together will let the existing architectures being exploited giving  parallel compute.

Llano has a graduated 11 layer metal stack with a variety of high  density SRAM cells to support both large caches and embedded compiled FRAMs in the GPUs, said Akrout.

One of the challenges for AMD are voltage limit trends as the process widths get smaller.  AMD, he said, will continue to push density. Power density has been slowed by BDD non-scaling and needs to figure out how to  overcome the challenges. It needs to unlock the benefits of TSV/Die  Stacking, and the industry needs together to invest in FinFETs, dense  memory and photonics. Memory needs to be denser because there are two  engines, the CPU and GPU to feed. Photonics needs to be implemented to  overcome bandwidth limitations, he said.

Packaging needs to improve with die stacking, giving better power and more performance at the interface of these chips. AMD will integrate eight cores in the 32 nanometre Orochi die, showing
 off the mysterious die but saying little more about it than that.